These pages provide links to people working on freeware EDA tools, and is the home page for a Freeware Verilog,VHDL and Analog Mixed Signal project (a.k.a. the V-2000 project - a work in progress*). If you were looking for System Verilog then you may or may not be in the right place too.

Should you be using C++, SystemC or SystemVerilog? The answer does (of course) depend on what your trying to do. If you are trying to write complex testbenches for Verilog designs then maybe SystemVerilog is for you (it's a no-brainer if you're already a Vera fan). If you are thinking of trying to do some software/hardware trade-off in the early stages of a design then maybe C++/SystemC will work better for you.
SystemVerilog (SV) currently does not support many features of C++, and although it may be "safer" to program it is a different language with limited vendor support - you won't find a compiler for your favorite embedded processor for the parts that end up software rather than hardware. It has no extensions which really address the problems of deep-sub-micron design, or support new synthesis methodologies. It also has various syntax/semantic oddities that make it difficult to do top-down design - i.e. SV modules (and interfaces) do not decompose easily into synthesizable/realizable Verilog.   More detail...